The present invention relates to interconnect structures and methods to generate interconnect structures that are part of integrated circuits and microelectronic devices. The invention is based on the utilization of two distinct lithographic steps to create a structure having three distinct patterns. By repeating these processes, unique interconnect structures having enhanced mechanical or electrical properties are described. Exemplary methods for the fabrication of such structures are enclosed.
The fabrication of Very-Large Scale Integrated (VLSI) or Ultra-Large Scale Integrated circuits (ULSI) requires an interconnect structure comprised of metallic wiring that connects individual devices in a semiconductor chip, to one another. Typically, the wiring interconnect network consists of two types of features that serve as electrical conductors: line features that traverse a distance across the chip, and via features, which connect lines in different levels. Typically, both the line and via features comprise conducting metal lines of aluminum or copper, and are insulated by interlayer dielectric, ILD, which is an electrical insulator such as silicon dioxide (SiO2), or fluorine or carbon doped silica film deposited by plasma enhanced chemical vapor deposition (PECVD).
For interconnect fabrication, a number of key factors must be considered including performance, reliability, and cost. The first factor, or performance of an interconnect structure, is significantly affected by signal propagation delays, which are proportional to the product of the metal resistance, R, and the interconnect capacitance, C, of the metallic vias and lines. Thus, in order to reduce these delays, it is advantageous to minimize both the resistivity of the conducting metal and the capacitance resulting inherently in the spatial relationship between the conducting metal, i.e., the metallic lines and vias and the inherent characteristics of the insulating material surrounding and disposed between the metallic lines and vias. Minimizing such capacitance may be achieved by implementing materials having lower dielectric constant (k).
Historically, the interlayer dielectric has been silicon dioxide with a dielectric constant (k) equal to approximately 4.2. Decreasing the dielectric constant of an insulating material (or dielectric) has the effect of decreasing a capacitance related to its use. Recently, there has been a significant effort for implementing dielectric materials having lower dielectric constants including fluorinated glass (k˜3.8), carbon doped oxides (k˜2.8), etc. in expectation of realizing reduced capacitance. To decrease the dielectric constant even further (k˜1.8-2.4), porosity has been engineered into insulator materials in order to replace a portion of the material with air (k=1). Finally, it has been proposed that the entire insulator may be substituted with air in regions between conducting metal lines (i.e., air bridge) to minimize the capacitance between these features.
The second key performance factor, or reliability of the interconnect structures is of critical importance for IC operation, e.g., VLSIs and ULSIs. Unfortunately, with the driving need to reduce the capacitance in interconnect structures, the mechanical robustness of the multilayer structures is being reduced by the use of these lower dielectric constant insulating materials. That is, the newer materials being used as insulators for their lower k undesirably exhibit lower modulus and strength. This becomes even a greater concern as porosity is added into the interlayer dielectric, or when air gaps are incorporated since the strength of the interconnect structure can be greatly compromised by the effects of lower modulus and strengths of the dielectrics used. Compromising the interconnect structures renders them susceptible to failure during the subsequent fabrication processes, affecting wafer yield.
The third key factor, or the cost for manufacturing the interconnect structures is important. Manufacturing a semiconductor, particularly a VLSI or ILSI design, is a complex process comprising multiple integrated sub-processes and operations. Integration schemes involving such excessive and numerous processes can be cost prohibitive. Lithographic processes can be especially expensive due to the combination of costs associated with tooling, masks, photoresists, developers, etc. For example, the inherent manufacturing cost for air gap fabrication in interconnect structures may be an important consideration as a third mask set is often needed to implement same in addition to the line and via mask set within intended regions.
For interconnect structures comprising copper lines and vias, the typical fabrication approach for a semiconductor design uses what is referred to as a “dual damascene process.” By a dual damascene process, lines and vias are patterned by lithographic processes into photoresists, and the photoresists transferred into the interlayer dielectric to create a structure having topographical features corresponding to each of these patterns. Metal containing liner (that serves as a copper diffusion barrier) and copper is then deposited onto the structure. The structure is subsequently polished down to the interlayer dielectric to remove excess from the structure. Commonly, a copper diffusion barrier that is an electrical insulator is then deposited upon the structure so formed. This process may be repeated multiple times to create the interconnect structure, which as mentioned serves as the wiring network for the microelectronics being fabricated.
One approach of the dual damascene process is a “via-first” approach. Applying a via-first approach includes that the lithography corresponding to the via fabrication is performed prior to that required for the line lithography. An example of such a via-first scheme or approach is described as follows with respect to the steps outlined in FIGS. 1a-1e. Referring now to FIG. 1a, first and interlayer dielectric (100), and optionally, a hard mask (200) are deposited on a substrate (10). The via lithography is performed, and the via pattern (50) is transferred into the interlayer dielectric by reactive ion etch. Next, and FIG. 1b shows that a via filling material (300) is applied in order to planarize the substrate surface, and an optional hardmask (400) may be deposited as shown in FIG. 1c. Line lithography is then performed on the structure so far, and a line pattern (70) is transferred into the interlayer dielectric (100) as shown in FIG. 1d. Finally, and as shown in FIG. 1e, a metal containing liner (500) and copper (600) is deposited into the structure, which is subsequently planarized by chemical mechanical polishing or planarization (CMP). A cap barrier (700) that serves as a copper and air diffusion barrier is then deposited. These series of steps are repeated to form a multilayered interconnect structure comprised multiple levels of lines and vias.
Numerous variations exist to generate these interconnect structures. However, in general the conventional approaches involve two separate lithographic processes to generate the via and line patterns that are distinct and different. In damascene processing, in contrast to subtractive aluminum technology, the dielectric material is deposited first as a blanket film and is patterned and etched leaving holes or trenches. In “single damascene” processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire “lines” respectively. In “dual damascene” technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both the via and line simultaneously, further reducing the number of processing steps. Thus, for each dual damascene level, a binary structure having distinct structures defined by the via and line patterning is usually afforded.
Approaches to generate ternary interconnect structures whereby three distinct features are defined by three separate lithographic processes (i.e., exposures) have also been proposed. Examples of this are interconnecting structures that are fabricated to include airgap structures or airgaps, which are patterned in a separate lithography step using known and conventional semiconductor fabrication techniques. For interconnects involving airgaps, this third separate lithographic process is generally required because airgaps must be omitted in regions within an interconnect design or structure where their inclusion would result in degraded reliability or mechanical failure of same. (Arnal et al, IEDM 2001). Consequently, such approaches are generally not manufacturable however as a result of added lithographic process which can be cost prohibitive. Furthermore, since three lithographic processes would be employed to add the airgap structures in specific portions of the interconnect structures, significant complications may result which may or may not be anticipated, including to name one, overlay misalignment resulting from the three separate patterning steps.